Thursday, August 28, 2008

Interview redux

Well after having ran out of time for a proper interview last time, the company managed to sort out transportation for me to get back down to Hamilton for that interview.  I had to wake up at 6 o'clock again to make a 7:40 am InterCity bus from the Sky Tower.  The toilets were third world standard.  Poo land.  There were 7 others on the trip down and took around 2 hours.  I was being a complete tourist and taking random pictures every so often.  When the bus got to the Hamilton bus stop, the first thing I looked for was an outlet for my memory leak.  The weather made for brisk walking.  The time was close to 10am.  So, come to Alexandra Street, I made my way into the KPMG tower and took the lift up to 9.  The lift stopped at level 7 and surprisingly the firmware manager stepped into the lift.  First thing I thought about was the elevator pitch but all I did was raise an eye brow to send an acknowledge signal and he basically did the same so he sent back a ready signal.  At this point we rendezvoused with a hand shake.  Must have been a random sight for the two others in the lift.  So we reached the 9th floor and I got a quick 10 min break to freshen myself.

So, just the firmware guy in a fume ridden room.  First thing to do was to go through the test.  Got asked what I meant when I had (counter + 1) / 16.  Probably wrong syntax but the division was supposed to act as a modulus so the counter value would be between 0 and 15 all the time.  Probably needed the percentage sign.  Next was that RTL diagram with the useless "and" gate that would always be false.  So got asked how I could optimise the circuit.  Simple, take out the and gate and operands.  Then the multiplexer becomes useless and because the binary counter is clocked, the output register is not needed.  Then assuming that the initial state of the counter is not important, you can remove the "+ 1" logic.  All you're left with would be an up counter.

Next question, to do with metastability.  This is where the self rooting comes into play.  First, if there is a 200M clock and a 50M clock and you wanted to transfer data at irregular periods from the higher clocked domain to the lower clocked domain, what problems will you have?  If you have a block in the middle of the two domains, what signals do you need?  How do they communicate?  Assuming that the downstream (50M clock) component can always accept data, what signals can we remove?  Draw the timing graph of a data transfer from the upstream to downstream component.  How would the middle component be able to match the two clocks so that there is no glitching due to each of the clock edges being too close together?  All I can say is that there were a lot of *silence* and stares at the board.  I think the interviewer was very good at hiding the fact that I was pissing him off with my stupidity.  Not enough focus.  So, that was probably the worse than the radio interview I had in year 2 where the lecturer kept saying I was wrong.

So, next question.  I think I had an advantage because I was told the same question after the first interview.  The objective is to make a mono-stable component.  The component accepts one pulse and outputs a long pulse.  The pulses are synchronous.  Since I knew a loop would be a fail, I used a variable to keep track of the down counting from 100,000.  The next question was, what would be synthesised?  Pretty much just a down counter with its 17 bit long output simplified down to a 1 bit number through bitwise "or".  The result of the "or" is the output.  No need to use compare logic.  A few control signals are needed and some use of precedence to get expected behaviour.  Much easier question.

The next thing on the list was just general questions.  What was the hardest thing you have come across?  What final year project are you working on?  Where did you learn VHDL from and what projects did you make?  The interviewer was writing quite a lot from the rather short answers that I was giving him.  I'm not very descriptive by nature when it comes to useful information.  Or maybe I'm able to "get to the point" super efficiently?

The interview concluded after about one and a half hours.  Not as long as the others.  Tough though.  There were also some Waikato University students there.  There were wearing similar outfits to one another.  I don't think they are a competition for us because they looked quite young.  Chances are they are only interested in a summer job.  One of the guys started a chat with me.  Started with the obvious question: Are you here for an interview?  Anyway, they didn't learn much about VHDL but they have used micros quite a bit.  They also learnt C# but nothing much apart from C for programming their micros.  They took the absurdly hard algorithm, C and Linux tests as well.

So anyway, the HR person escorted me to the QuickCat shuttle and luckily we got there in time because the driver was already outside waiting and had already phoned saying that I was not there.  There was one other passenger inside and they were going to the airport.  Sounded like they came from Ireland.  Got back to Uni at about 3 pm and started panicking for the 704 presentation.  But first, had to go to the Marae for 403.

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