CompSys704

The last instruction of each task is a task complete instruction which stores the context of the task when it is executed again. Can compare two input signals in the Reactive Functional Unit.

Hybrid Reactive Architecture is biased towards FPGA implementation because of the use of embedded shared memories. Allows the integration of application specific programmes which is hardware with ReMIC which is software.

SystemJ: Java + Esterel + Communicating synchronous processClick domains connected with asynchronous channels. Java is non-deterministic but has threading support. Each clock domain contains reactions which are sequential instructions combined concurrently with signals between each other. SystemJ source code is translated to hardware and software components throgh Asynchronous Graph Code.

Composed and transmitted from my iPod Touch