About Me

Monday, May 10, 2010


  • Simulation examples (Hardship)
  • Bandwidth of copper wire doesn't keep up with bandwidth of processors.
  • Latency of conducts not improving.
  • Fibre optics not very fast. Only air core; but increases available bandwidth.
  • mpi_reduce >> mpi_waitall, mpi_reduce, mpi_barrier, mpi_recv.
  • Ethernet chip to offload communication.
  • Memory chip speeds have not increased.
  • Bandwidth/Latency.
  • Linux -> Computer frontend -> Matrix of computing resources.

Experience with and potential of hardware transactional memory

  • Rock processor
  • Everyone needs to do concurrent programming. Not just OS or VM developers.
  • Essence of TM: ability to access multiple memory locations in an atomic transaction, without specifying how atomicity is achieved.
  • Using one lock: not scalable but mimicks transactions. Parallel critical sections.
  • Finer grained locking.
  • Best effort hardware transactional memory - Hardware can abort. Problems raised to the software level.
  • Abort feedback important.
  • Speculative haredware features gave subtle bugs.
  • Lock elision.
  • Doubled ended queues.