About Me

Showing posts with label systems. Show all posts
Showing posts with label systems. Show all posts

Sunday, July 10, 2022

Intel DE10 Nano FPGA Board: Using the Deprecated Altera VIP Frame Reader

I have the DE10-Nano Kit from Terasic, which has a chip with FPGA fabric together with a dual-core ARM processor. You can run Linux from an SD card just like a mini computer system. I have been wanting to update the Linux kernel (version 4.14) and the FPGA hardware design, which now uses outdated Altera design IP for the frame buffer. 

Terasic offers example Linux set ups and hardware design files, but these have not been updated for a few years and use old Linux kernels and old Quartus projects. Graphical output is possible via the HDMI port, but Linux needs to use a frame buffer to store each video frame. The Altera Video Image Processing (VIP) Frame Reader for graphics output was last updated in 2014 and is now deprecated. Moreover, support for this hardware component was dropped from the Linux kernel at the start of 2020. The successor is the Intel Video and Image Processing (VIP) Frame Buffer II, but this IP requires a paid license without tether or time limits. I could not figure out the process of purchasing the IP, because all the web links led me in a circle with no offer of a web form or sales contact. In summary, it just seems like a dead end for my hobby purposes.

I decided to keep using the deprecated Altera Video Image Processing (VIP) Frame Reader, and to instead update to a more recent Linux kernel (version 5.15.30) with the hope that I could patch back the kernel module for the Altera VIP Frame Reader, called altvipfb. My first attempt was to simply revert the reversion. This did not work, and I got a stack trace during boot up when the altvipfb module was being loaded (altvipfb_probe).

My next attempt was to look at the source code of the altvipfb2 module (altvipfb2.haltvipfb2.caltvipfb2-plat.c), which is the successor to altvipfb, in the hope that the code would be similar enough to help give me clues as to how to modernise altvipfb's usage of the frame buffer API. Luckily, this was the case and I was able to reorder the initialisation sequence of the module and update a few API calls and have the altvipfb driver working! A summary of the changes can be found in my gist:

Wednesday, August 18, 2010

Concurrent Python using transactional memory

Speaker: Fuad Tabba

"Parallelism is hard"
  • Figure out the parallelism in the application.
  • Figure out the required synchronisation. How do you protect the critical sections? Race conditions, deadlocks, livelocks. Locks take away the parallelism you had hoped to achieve.
  • Locks have inherent overhead.
Python uses one "Global Interpreter Lock" to protect shared resources.

Transactional memory: Atomicity, Consistency, Isolation, Durability.
The use of transactional memory is to abstract away critical sections so that parallel programs can become easier to write.

In the Sun Rock Processor (which has limited hardware support for transactional memory), there are two caches:
  • L1 Cache tracks memory locations that have been read and written to.
  • Write buffer stores tentative writes (uncommitted transactions).
Cache coherence protocol is used to detect transaction conflicts. The physical size of the caches limit the size of the transactions. When a transaction is committed, the new values have to be propagated to each processor. Transactions can abort/fail for unspecified reasons.

Friday, September 26, 2008

CompSys704

Had my presentation today for some research I had done. Was going well untill the 8 min mark hit and I was only half way through my slides. Had to miss a large chunk of material that would have been more interesting. Ah well at least one of my lecturers offered one of his lecture slots for me to present my whole lecture again.

Composed and transmitted from my iPod Touch

Thursday, July 24, 2008

Three day lecture summary

Since I've only started blogging late yesterday night, I thought I'd make a very quick summary of my lectures three days into semester two. Exciting I know ...

EngGen403
(Communication is important)^100. Missed out on lecture notes because I came late and people were late to enrol so not enough notes were printed off. There was a drunk guy in class and he was sitting in the back corner and he basically communicated his thoughts on sustainability through his constant laughter. The course co-ordinator gave a pre-compiled speech for us to listen too. Didn't like it very much because it was too rehearsed and not personal enough. He went through the course content and the guest lecturers involved. A speaker from BECA came and gave a general overview on communication in the work place. The importance of understanding sentences used and the habits of generalisation and misrepresentation. The 24 hour rule to make sure you have interpreted an email correctly. The hidden risks of giving friendly advice as a professional engineer. The role of an engineer as being more than someone fixing things; we provide advice as consultants.

CompSys704
Came to the lecture late again. No girls in the class room. Sad. A guy in our class has an iPhone 3G and Zoran proceeded to ask them what sort of embedded communication devices it had. Went through the course and list of special topics to research on. Still have to pick mine but will probably try and get a real-time topic. Or one that focusses on handling real-time commands and handles them through sorting/ordering as a form of precedence. Might look into Erlang as a possible language to do modelling. Erlang is a programming language which has many features more commonly associated with an operating system than with a programming language: concurrent processes, scheduling, memory management, distribution, networking, etc.

ElectEng426
Still wasn't sure if I wanted to do digital communications since I know I'm bad with signals and fourier transform. The first lecturer was quite monotonous but if you concentrate a little, he is interesting. Yet more assumptions about the signals being modelled. Additive noise and uncertainty of the voltage received. Went through the usual block diagram from reception, sampling, detection and decision. Missed out on the second lecture because of the EngGen 403 test.

Fin251
A just for fun paper. Went through what makes a corporate. Agency conflicts and remedies. Market value. Book value. Calculation of interest. Present value. Future value. Annuity. Pretty basic things that "Management for Engineers" has taught us already. It'll be interesting if the lecturer talks about markets and that it is speculative and no one is wiser than any other.