Monday, May 10, 2010

Experience with and potential of hardware transactional memory

  • Rock processor
  • Everyone needs to do concurrent programming. Not just OS or VM developers.
  • Essence of TM: ability to access multiple memory locations in an atomic transaction, without specifying how atomicity is achieved.
  • Using one lock: not scalable but mimicks transactions. Parallel critical sections.
  • Finer grained locking.
  • Best effort hardware transactional memory - Hardware can abort. Problems raised to the software level.
  • Abort feedback important.
  • Speculative haredware features gave subtle bugs.
  • Lock elision.
  • Doubled ended queues.

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