Custom Instruction, Avalon MM Slave, Verilog

Managed to get a custom instruction to work without much incident which was a shocker.  Didn't think I was up to the task.  Just have to make sure to specify appropriate interface signals like "custom_instruction_slave".  System generation and synthesis was pretty easy.  Using the new custom instruction was also easy as it's exposed as a #define-d macro in the System.h file.

I also managed to create my own Avalon MM Slave component.  Just had to specify the necessary slave interface ports and test that the component was behaving as expected before making my own SOPC component for use in a system.  It worked first time so I was very happy that I didn't have to trouble shoot anything.

In extending my Avalon MM Slave component, I hit a few behavioural bugs and I'm not sure if it's because I don't understand Verilog enough or because of a problem in the synthesised circuit.  My problems/glitches mainly came from the use of multiple edge triggered signals in a sensitivity list and the assignment of asynchronous signals in a clocked always body.