Python, CherryPy and Verilog

Decided to try and upgrade Python from 2.52 to 3.0 on my Xubuntu partition.  I decided to try and install all the packages in a bid to try and get rid of all the module warnings.  I did succeed in the end but I probably installed a lot useless sources.  Took ages trying to find the right sources to install as well.  Anyway, got Python 3.0 to compile and install so that was good.

Now I know that CherryPy 3.1.1 is incompatible with Python 3.0 so I was prepared to manually "update"/hack the source files of CherryPy so that it would run.  I was quite successful in updating the syntax and finding replacement modules to use in place of the depreciations.  A lot of the changes were just guesses though because some of the Python 2.x syntax looked quite "loose"; especially the the except and raise expressions.  However, the new module "socket" that replaces "Socket" had changed quite a lot so I was unable to find the updated method calls.  Namely, I couldn't find an equivalent to socket._fileobject(None)._rbuf in Python 3.0 so that was when I gave up on "updating" CherryPy.  I *think* I found something similar called makefile() but the resulting object doesn't have an _rbuf attribute.  Not entirely sure what _rbuf stands for.  Could be "receive buffer".  I think the point of the line is to get a file object expected by the socket in its receive buffer and try and find out what type of object it is.  Guess I'll just have to wait for the official implementation.  Could be a few years . . .

Tried some more Verilog.  Stuck on how you should statically define an array.  Right now I've only got the array *initialised* within the "always" block which to me is clearly the wrong place; but it works okay for now.  There's also the distinction of packed and unpacked arrays which concerns the layout of memory.  Also, I'm not sure how you specify the range for an integer.